Circuit arrangement for taking the mean of several input voltages

ABSTRACT

A control apparatus has redundant input signals from which an output signal is produced. There is an input for each input signal respectively and a double-pole between the respective input and the common output. Each double-pole defines a predetermined magnitude of signal that it will pass and predetermined resistance below the threshold so as to limit the extent of the voltage step at the output by interference in a respective channel.

limited States Patent [191 Matejka Sept. 18, 1973 CIRCUIT ARRANGEMENT FOR TAKING THE MEAN OF SEVERAL INPUT VOLTAGES Edgar Matejka, Singen/Hohentwiehl, Germany Bodenseewerk Geratetechnik GmbII, Uberlingen/Bodensee, Germany Filed: Sept. 20, 1971 Appl. No.: 181,819

Related US. Application Data Continuation of Ser. No. 175,581, Aug. 27, 1971, abandoned.

Inventor:

Assignee:

Foreign Application Priority Data Sept. 18, 1970 Germany P 20 46 140.9

US. Cl 328/158, 307/219, 307/237, 307/304, 328/171 Int. Cl. H03k 5/08, H02h 7/20 Field of Search 307/219, 235, 237, 307/304; 328/117, 171, 137, 154, 158; 340/1461 BE References Cited UNITED STATES PATENTS l/l970 Woodward, .Ir. 307/219 X Primary Examiner.lohn W. Huckert Assistant Examiner-L. N. Anagnos Attorney-Howard H. Darbo et al.

[ ABSTRACT A control apparatus has redundant input signals from which an output signal is produced. There is an input for each input signal respectively and a double-pole between the respective input and the common output. Each double-pole defines a predetermined magnitude of signal that it will pass and predetermined resistance below the threshold so as to limit the extent of the voltage step at the output by interference in a respective channel.

4 Claims, 9 Drawing Figures 4 Shea ts-Sheet 1 FIG. 2

IN VEN TOR fps/ 15 M4 TEJKA P fim 62 Patented Sept. 18, 1973 3,760,284

4 Sheets-Sheet 2 E U1 Z 1 Z 5 UM E A U2 .2 Z A2 E U3 Z FIG. 3

INVENTOR EDGAR MA TEJ/(A Patented Sept 18, 1973 4 Sheets-Sheet 5 A1 ouTPuT VOLTAGE AT A| 4. om INPUT VOLTAGE I DEVIATION U AT E| FIG. 4 a

L\2ouTPuT VOLTAGE AT A2 "AUOS Uf om INPUT VOLTAGE I DEVIATION I Im AT E| UA3 OUTPUT VOLTAGE AT A os nu om INPUT VOLTAGE DEVIATION im AT E FlGlIc Patented Sept. 18, 1973 4 Shoots-Sheet 4 FIGS CIRCUIT ARRANGEMENT FOR TAKING THE MEAN OF SEVERAL INPUT VOLTAGES The present application is a continuation of [1.8. application Scr. No. l75,58l, now uhondoned.

BACKGROUND AND SUMMARY OF THE INVENTION.

My prior U.S. Pat. No. 3,697,776 issued Oct. 10, 1972, relates to a circuit arrangement for taking the mean of several input voltages. The input voltages are applied through resistor branches to a common load resistor across which the mean value (the term mean being used herein in the sense of an arithmetic mean) output voltage appears. The resistor branches are controlled in dependence on the difference between the output voltage across the load resistor and the respective input voltage of the branch in such a manner that this input voltage will be suppressed if it deviates by more than a given degree from the output voltage. Circuit arrangements of the type indicated are used, in redundant systems, to take a mean from different measuring or control signals, with out of place" signals being suppressed. The prior patent aims at effecting such a contactlessly suppression of out-of-place input voltages. According to said prior patent, this is achieved in that the resistor branches comprise voltage-dependent double-poles designed with semiconductor elements, whose resistance becomes very great above a voltage threshold. Below this voltage threshold, the resistance value of the individual resistor branches is as small as possible.

The emodiments described in said prior patent involve problems. For example, with a sudden change of one of the input signals (thus, if the voltage across the respective double-pole suddenly exceeds the voltage threshold and therewith this resistor branch is practically switched off) a signal step occurs across the output of the circuit arrangement. This signal step may have an amplitude which will maximally assume the value of the difference of the two remaining intact signals. Such signal steps can have highly undesirable and dangerous consequences, for instance in an automatic pilot.

It is an object of this invention to reduce dangerous signal steps of the described type in a circuit arrangement of the character of said patent.

The invention is based on the discovery that in such circuit arrangements for taking the mean it is necessary to dimension the voltage-dependent double-poles in a specific manner. Accordingly, the said object is solved by using an output voltage threshold (U,) defined by the formula:

U, (n-l/n) A U,

where n is the number of inputs, i.e. respectively resistor branches. A U, is the tolerance for the maximal occurring output signal step in a single channel if there is an interference in that channel. Obviously for every A U,. at the output of a channel there is a corresponding A U at the input of the channel (i.e. A U,,, is a function of A U The resistance R of each double-pole has a finite value below the voltage threshold ofabout where 1,, is the required maximal output current of the circuit arrangement.

DESCRIPTION OF THE DRAWINGS FIG. I illustrates the basic circuit used for n input signals;

FIG. 2 shows the characteristic of a voltagedependent double-pole of FIG. 1;

FIG. 3 shows a corresponding circuit arrangement for three input signals and three output signals;

FIGS. 4a to 40 show the output voltages across the three outputs of FIG. 3 in dependence on the deviation of the input voltage across one of the inputs;

FIG. 5 shows an embodiment of a voltage-dependent double-pole according to this invention;

FIG. 6 shows another embodiment of a voltagedependent double-pole; and

FIG. 7 shows a third embodiment of a voltagedependent double-pole.

DESCRIPTION OF SPECIFIC EMBODIMENTS The following disclosure is offered for public dissemination in return for the grant of a patent. Although it is detailed to ensure adequacy and said understanding, this is not intended to prejudice that purpose of a patent which is to cover each new inventive concept therein no matter how others may later disguise it by variations in form or additions or further improvements. The claims at the end hereof are intended as the chief aid toward this purpose, as it is these that meet the requirement of pointing out the parts, improvements, or combinations in which the inventive concepts are found.

FIG. 1 shows the basic circuit used for n input signals. In this circuit, the input signals U, to U, (applied at inputs E, to E, respectively) are transmitted to a common output point A through special double-poles Z to Z,,. In order to permit the illustrated basic circuit to operate functionally correct, the double-poles must have the characteristic illustrated in FIG. 2. The characteristic shows that the double-poles are voltage-dependent. For a voltage applied across the double-pole, the double-pole resistance R shall be For a voltage applied across the double-pole, however, the current I through the double-pole shall be limited to the value R U,/I,,

is calculated.

FIG. 3 illustrates a complete circuit arrangement for three input signals U,, U,, U,, for respective output signals U U U In this case the basic circuit illustrated in FIG. 1 and having three inputs E E E is used three times in order to obtain three outputs A A A In the FIGS. 4a, 4b, and 4c, the three output voltages U U U (at outputs A A and A; respectively) are illustrated in dependence on the input voltage deviation A U It was previously shown that up to the maximum permissible signal deviation AU (input variation) the double-poles have the resistance R. From this condition U, is obtained. Under the condition illustrated in FIG. 3 where there are three groups: U U: A U U U; U (U being the normal voltage) U A U- For n inputs U, (n-l/n) A U. is obtained The FIGS. 4a to 4c illustrate the three output signals as a function of a variation in one of the input signals (e.g. that at E and show that the output signals of the circuit arrangement are identical. If the signal deviation exceeds the value A U at the input E then the output signals U U and U will no longer be influenced by it. The maximal signal deviation at the outputs A A A, based on the signal deviation at the input is A U,,,/3 or A U,,,,,; A U being the deviation in the output of a multichannel arrangement, i.e. FIG. 3, and is a function of the deviation of the input signal A U in one channel of that multichannel arrangement. Since A U, and A U are functions of each other and U (n-l/n) A U it follows that:

U =(n-1/n A U,

As the circuit with respect to input and associated output is always designed in the same manner, the identical results are obtained for the other two inputs.

The reflections hereinbefore were made without a load. The permissible load current is maximally I,,. It effects an output signal deviation by maximally 0.5 U, at the outputs.

The following are examples of double-poles:

1. Cold conductors A cold conductor is a temperature-dependent resistor having very low resistance below the Curietemperature and a high positive temperature coefficient above the Curie-temperature. The resistance of a cold conductor can be changed by means of the current flowing therethrough. As the change in resistance is effected through the by-pass of temperature, also the ambient temperature influences the break in the characteristic. It is therefore recommended that a stabilization for the ambient temperature be provided. In order that the resistance R of the double-pole can be adjusted in a defined manner, a balancing resistor R, must be connected in series with the cold conductor.

2. Circuit arrangements with field effect transistors The circuit illutrated in FIG. 5 employs a symmetrical field effect transistor FTl as the main component of a voltage-sensitive double-pole such as might be used in each resistor branch Z. The symmetrical field effect transistor has a pair of preceding and succeeding resistors R Its gate is connected through diodes D,, D with the free end of the resistors. A balancing resistor R is in series-connection in this circuit to make up the remainder of the total resistance R. This double-pole circuit also has the necessary characteristic. Herein, the low resistance range is substantially determined by the properties of the field effect transistor FTl. To make up the required resistance R, the balancing resistor R is used. The adjustment of the current limitation I, is accomplished by means of the resistors R Advantageously, field effect transistors with low drain-source resistance (r and small pinch-off" voltage are used.

Another cirucit including field effect transistors is shown in FIG. 6, in which the double-pole of each resistor branch Z comprises a pair of field effect transistors (FTZ, FT3) connected back-to-back (antiparallelly) by resistors R The gate of field effect transistor FT3 is connected through a resistor R, with the source of the transistor FT2 and the gate of the transistor FT2 is connected by a resistor R with the drain of transistor FT3. A balancing resistor R, is arranged in series-connection in this circuit to make up the total resistance R. Herein, the current I, is adjusted with the resistors R the resistance R with the resistor R 3. Circuits with operational amplifiers If very accurate values for R and 1., are to be provided the use of four-pole circuits, the transfer characteristic of which corresponds to that of the double-poles, are recommended. In these circuits, operational amplifiers are preferably used. An example for such a circuit to form a resistor branch Z is shown in FIG. 7. Utilizing a field effect transistor double-pole of the type discussed in connection with FIG. 5, its input is connected to the output of an operational amplifier V. The output P of the double-pole is connected to the input of the amplifier by a feedback resistor R providing a negative feedback. The branch input E is connected by a resistor to the amplifier input by a resistor R The branch output A is connected to P by a resistor R which serves to make up the desired total resistance R. The FIG. 5 double-pole (P'Il', R' D and D',) provides current limiting in the series circuit between input E and output A.

Of course, also other circuit arrangements are known which can be used herein to provide current limitation, a condition being that the current limitation is effective in a bipolar manner. The negative feedback of the amplifier according to the current limiting circuit is derived at the point P and is applied via the feedback resistor R to the sum point (input) of the amplifier. The input signal U is also applied to the sum point via the input resistor R Due to the negative feedback the source impedance is very small and can be neglected, when the amplifier is operated on its characteristic. Then, the source impedance at the output point A of the arrangement is determined only by the resistance R which connects the point P with the point A. Therewith, the resistance R, can be selected in accordance with the requirements of the circuit arrangement of the invention and generally corresponds to the resistance R.

It may also be mentioned that the wiring of the operational amplifier can substantially be selected as desired. Thus, special frequency characteristics also can be achieved.

I claim:

1. In an apparatus for use with a plurality of channels and of the type for forming the mean value of several input voltages from said channels, said apparatus havwhere n is the number of inputs of respective resistor branches and U is the tolerance for a maximal occurring signal step in said mean value when there is interference in a channel, and the resistance R of each double-pole has a finite value below the voltage at said threshold of about where 1,, is the required maximal output current at said output.

2. In an apparatus as set forth in claim 1, wherein each doublepole includes:

a symmetrical field effect transistor having three connections a first of which is'a gate connection, a

diode and a resistor connected in series between the first and a second of the transistor connections with a first juncture therebetween, a diode and a resistor connected in series between thefirst and third of the transistor connections with a second juncture therebetween, a balancing resistor, said junctures and said balancing resistor being connected in series between the respective input and output of the double-pole.

3. In an apparatus as set forth in claim 2 wherein each resistor means includes an operational amplifier having an input and an output connected in the series circuit between said input and output of the respective resistor means, the amplifier output being connected to the first juncture, a negative feedback circuit including a resistor connecting the second juncture with the amplifier input, and a resistor connecting the amplifier input to the input of the respective resistor means.

4. In an apparatus as set forth in claim 1, wherein each voltage sensitive double-pole includes a pair of field effect transistors connected back-to-back by a pair of resistors and connected in series with a balancing resistor between the input and output of the respective resistor means.

l t 4* l U ITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3, 32 Dated September 18, 1973 Inventor(s) Edgar Matejka It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Col. 2,Line.42 should read Col. 3, Line 26 After "input" should "b'iri'serted E Col. 4, Line 11 "cirucit" should read --circuit- Signed and sealed this 21st day of May 197M.

(SEAL) Attest:

EDWARD 1-I.I+LETCIIEH,JR. I C. MAI- SHALL DAMN Attesting Officer Commissionerof Patents ORM PO-1050 (10-69) USCOMM-DC 60376'P69 fl' U.S. GOVERNMENT PRINTING OFFICE 1969 0B66-33l, 

1. In an apparatus for use with a plurality of channels and of the type for forming the mean value of several input voltages from said channels, said apparatus having a plurality of inputs at which said input voltages are applied respectively, an output at which said mean value appears and a plurality of resistor means with each resistor means connecting a respective input with the output, and wherein each resistor means comprises a voltage dependent double-pole whose resistance becomes very great above a threshold, the improvement comprising: said voltage Ut at said threshold being Ut (n-1/n) Delta Uo where n is the number of inputs of respective resistor branches and U is the tolerance for a maximal occurring signal step in said mean value when there is interference in a channel, and the resistance R of each double-pole has a finite value below the voltage at said threshold of about R Ut/Io where Io iS the required maximal output current at said output.
 2. In an apparatus as set forth in claim 1, wherein each double-pole includes: a symmetrical field effect transistor having three connections a first of which is a gate connection, a diode and a resistor connected in series between the first and a second of the transistor connections with a first juncture therebetween, a diode and a resistor connected in series between the first and third of the transistor connections with a second juncture therebetween, a balancing resistor, said junctures and said balancing resistor being connected in series between the respective input and output of the double-pole.
 3. In an apparatus as set forth in claim 2 wherein each resistor means includes an operational amplifier having an input and an output connected in the series circuit between said input and output of the respective resistor means, the amplifier output being connected to the first juncture, a negative feedback circuit including a resistor connecting the second juncture with the amplifier input, and a resistor connecting the amplifier input to the input of the respective resistor means.
 4. In an apparatus as set forth in claim 1, wherein each voltage sensitive double-pole includes a pair of field effect transistors connected back-to-back by a pair of resistors and connected in series with a balancing resistor between the input and output of the respective resistor means. 